Journal paper
Entry Year101
Paper title (chapter)Load-Balanced Clock Tree Synthesis with Adjustable Delay Buffer Insertion for Clock Skew Reduction in Multiple Dynamic Supply Voltage Designs
Name of journalACM Trans. on Design Automation of Electronic Systems
Date of publication2012-06
number of chapters17
Issue No.3
Total number of pages22
Name of author (Chinese)Chia-Chun Tsai
Name of author (English)Chia-Chun Tsai
上傳檔案名稱2012_0615-ACM TODAES-MDSV-Clock-in ADB.pdf
Language used外文
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